dangitsegfault/verilog-traffic-controller
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2023-06-12 01:23:36 +05:00
code Changed program finish from 1300 units to 1500 units 2023-06-12 00:56:25 +05:00
pics First working code 2023-06-11 23:44:18 +05:00
LICENSE Initial commit 2023-06-11 23:30:55 +05:00
project_report.pdf Add files via upload 2023-06-12 01:23:36 +05:00
README.md Initial commit 2023-06-11 23:30:55 +05:00

README.md

digital-system-design-traffic-controller-project